Phase Lock Loop (PLL) circuitry often finds application in locking an internal clock signal to an input/output (I/O) clock signal by achieving phase alignment between the internal clock signal (internal clock) to the I/O clock signal (I/O clock). By using a PLL to lock an internal clock to an I/O clock, a clock generation system (that is generating the internal clock) can ensure that the internal clock is within the required frequency range before enabling downstream circuits or transmitting data. Generally, the lock declaration needs to be accurate and achieved with low latency to prevent adding startup time to a larger system that is using the clock generation system.
Traditionally, a clock generation system can use one or more digital counters to measure frequency difference between an input clock signal (e.g., I/O clock) and an output clock signal (e.g., internal clock). In particular, the clock generation system may compare the counts of two clock signals for a short period and declare lock if the two clock signals are sufficiently close to each other. However, due to clock speed limitations, this traditional digital-counter method cannot achieve both high accuracy and low latency. For instance, a current implementation of this traditional digital-counter method may require two iterations to declare a lock and may have a minimum of +/−2 steps of error. Due to the high level of error in the lock determination, a lock wait time has to be set to the max expected lock time with margin of error. Additionally, if the output clock signals contain spread-spectrum or similar modulation, the use of high speed clocks to reduce latency and improve accuracy can be much less effective.